1. Field of the Invention
The present invention relates to a FIFO buffer used as a buffer for buffering signals waiting for processing in the signal processing or as a buffer for absorbing collision in an interconnection network of an exchanger, and more particularly, to a photonic frequency division multiplexed FIFO buffer used in an optical computer or an optical exchanger for processing high speed optical signals.
2. Description of the Background Art
As a photonic buffer using a wide bandwidth optical delay line, and especially as a photonic FIFO buffer for connecting signals from a plurality of input highways to a single output highway, there has been a configuration as shown in FIG. 1, in which a one input one output FIFO buffer is provided for each input highway. More specifically, this configuration of FIG. 1 comprises: an input highways 1-1-1 to 1-1-M, signal discarding lines 1-2-1 to 1-2-M for discarding signals from the input highways 1-1-1 to 1-1-M, respectively, one input one output FIFO buffers 1-3-1 to 1-3-M connected with the input highways 1-1-1 to 1-1-M, respectively, an M.times.1 switch 1-4 connected with outputs of the one input one output FIFO buffers 1-3-1 to 1-3-M, and an output highway 1-5 connected with an output of the M.times.1 switch 1-4.
In this configuration of FIG. 1, the time division signals on each of input highways 1-1-1 to 1-1-M are separately buffered by the respective one input one output FIFO buffers 1-3-1 to 1-3-M provided in corresponding to the input highways 1-1-1 to 1-1-M. The M.times.1 switch 1-4 selects only one of the output signals of the one input one output FIFO buffers 1-3-1 to 1-3-M and outputs the selected output signal to the output highway 1-5.
Here, each of the one input one output FIFO buffers 1-3-1 to 1-3-M can be constructed in a configuration shown in FIG. 2, as described by R. A. Thompson in "Optimizing Photonic Variable-Integer-Delay Circuits", Topical Meeting on Photonic Switching, Mar. 18-20, 1987, pp. 141-143. More specifically, this configuration of FIG. 2 comprises: an input line 2-1, 1.times.2 switch 2-2 connected with the input line 2-1, a signal discarding line 2-3 connected with the 1.times.2 switch 2-2, a plurality of 2.times.2 switches 2-4-1 to 2-4-R connected in series with the output of the 1.times.2 switch 2-2, loop shaped optical waveguides 2-5-1 to 2-5-R attached to the 2.times.2 switches 2-4-1 to 2-4-R, respectively, and an output line 2-6.
In this configuration of FIG.2, each of the loop shaped optical waveguides 2-5-1 to 2-5-R has a circumferential length equal to a unit length for switching of the signals, such that each loop functions as one buffer. The 2.times.2 switches 2-4-1 to 2-4-R are controlled such that any newly arriving signal is stored in an empty loop closest to the output side, and whenever the signal stored at the last (closer to the output side) loop 2-5-R is outputted, all the other signals stored in the other loops are forwarded to next loops. The signal arriving when all the loops are filled by the signals is going to be discarded by the 1.times.2 switch 2-2 through the signal discarding line 2-3.
In such a conventional photonic FIFO buffer, there has been a problem that it is necessary to provide a number of loop buffers for each input highway in order to satisfy the prescribed cell loss probability, so that a large number of buffers are required in each photonic FIFO buffer.